Supports Keystone distortion, Barrel and Pincushion distortions and Arbitrary distortions.New IP: Warp Processor for digitally manipulating images .HDMI2.1 (controlled access) adds support for Dynamic HDR, and enhanced gaming features (VRR, FVA, QMS and ALLM).DisplayPort Subsystems add support for HDCP2.2/2.3 repeater feature.CSI TX subsystem adds support for YUV422 10bit.SEM IP core device support additions for US+ devices.XilSEM library API release & documentation in UG643.SmartConnect support for non-power-of-two address ranges.AXI IIC improvement to dynamic read mode function.CPM4 support in Versal CIPS Verification IP (VIP) for simulation.Early access support for CPM5, PL PCIE5, and GTYP in Versal Premium.Preservation of metadata in these packaged IPs for Vitis kernel usage.Kernel specific DRCs within IP packager.Production release for packaged RTL IP as Vitis kernel.Ability to tag files as SV or VHDL-2008 in the packager from package an IP from a directory.Connectivity of custom interfaces in IPI / Custom IP.Packager customer experience improvements.IPI now supports non-power-of-2 (NPOT) address assignments across Address Paths with one or more SmartConnect IP.Non-Power of 2 DDR Assignment through Interconnect.Allows easier creation of designs that access all available memory connected to the device or on the board, e.g. DDR and LPDDR.Enables intuitive Block Automation for NoC & CIPS connectivity.IPI Designer Assistance for CIPS & NoC.Syntax Errors and Warnings as you type.IP Re-architecture of CIPS to Hierarchical Model.Migration of older Vivado projects to new directory structure.3rd party board partners can contribute to these repositories asynchronously to Vivado releases.Download boards and example designs from GitHub.Address management for BDCs from the Top-level BD.Ability to specify variants for simulation and synthesis .Enables Modular Designing for Reusability. 2021.1 is the production release for block design containers.This viewer shows the runtime profile of your design and allows the user to remain in the Vitis HLS GUI. All functions and loops are shown along with their simulation dataĪ new Timeline Trace Viewer is now available after simulation.New Overview feature that shows the full graph and allows the user to zoom in on parts of the overall graph.New mouse drag based zoom in and out capability.The Function Call Graph Viewer has some new features: Text version of bind_op and bind_storage reports are provided.Some of these properties have associated user controls which should be reported to users.Interface adaptors have variable properties that impact design QoR.Users need to know the resource impact that interface adaptors have on their design.Improve HLS timing estimation accuracy: When HLS reports timing closure, the RTL synthesis in Vivado should also expect to meet timingĪdd interface adaptors report in the C synthesis reports:.Provide support for users to input high-level throughput constraints.Ultra HD 8K multimedia solution enablement for. Versal AI Edge enablement of soft IPs and Video Decoder Unit (VDU).QDMA v5.0 improved performance/resource utilization.Versal CPM Tandem PCIe Design (from CED Store).Versal CPM5 PCIe BMD Simulation Design (from CED Store).CPM5 x86 host drivers for Linux and DPDK in public release on GitHub.Zynq RFSoC DFE O-RU TRD: Updated w/ Low PHY processing only.Zynq RFSoC DFE DPD Update: PL resource reduction.Zynq™ RFSoC DFE IP Update: Channel Filter and DUC-DDC UL/DL sharing.Added support for 16 lanes of GTYP or Gigabit Transceiver Module (GTM) on Versal Premium.
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